July 2, 2022
  • July 2, 2022

Speculation on the future development of the FPGA

By on June 13, 2022 0

For the development of FPGA technology, the acquisition of Xilinx and Altera by AMD and Intel respectively is obviously an important turning point in this story. With the transition of the FPGA company from an independent company to a sub-department of the chip giant, its technology development strategy will also change significantly. This article will provide a perspective for the development of this strategy.

First, with the integration with chip giants, the FPGA will be further integrated with traditional chips to give full play to its programmable advantages to enable new capabilities of traditional chips and even realize new categories of chips.

New types of FPGA-compatible chips

For Intel, an example of such a new category of chips is the IPU (Infrastructure Processing Unit). With the heavy utilization of the data center, some important tasks in the data center, including network control, storage management, and network security, also have an increasing demand for processing capacity. While major chip companies are launching their own solutions, Intel has also launched the IPU for this market. Last month Intel just released its roadmap for the future of the IPU, in which we see that the IPU in the future until 2026 will consist of two versions, one is a high performance version based on ASIC, and the other is a programmable version based on FPGA (including Oak Springs Canyon in 2022, Hot Springs Canyon in 2023/2024, and the draft version in 2025/2026). Among them, the FPGA version-based IPU is actually an accelerator board integrating an Intel FPGA chip and an Intel Xeon processor. It can handle various network, storage and security protocols flexibly, to ensure maximum programmability without worrying about compatibility.

In fact, for FPGA solutions similar to data center storage and networking, startups have engaged in related projects over the past few years. However, with the admission of the giant Intel, we believe that such fpga+cpu solutions will really become one of the mainstream solutions. The fact that start-ups are engaged in relevant projects and obtain funding shows that the technical direction is feasible, and Intel’s entry into this market has brought green resources that start-ups do not have. We believe that in the next few years, FPGAs and CPUs will be more tightly integrated (eg, chiplet), to truly transform the flexible and programmable IPU into a new class of FPGA-enabled chips.

Coincidently, AMD is also actively considering integrating by Xilinx FPGAs and AMD CPU – to AMD earnings conference in May, CEO Lisa Su announced that it will release a Xilinx AI engine-integrated processor in 2023, that is, a processor with powerful AI computing power. Until now, AI-related computation has been performed in a GPU or other dedicated acceleration hardware. Intel’s previous efforts to optimize CPU-based AI have not been widely recognized by the market, as long as the number of CPU computing units is limited. However, since the overall AI task is not only a neural network, but also other parts of the program execution running on the CPU, if the CPU and the AI ​​acceleration unit can be tightly coupled, the overall performance of the task will be improved. It is also believed to be the original intention of AMD offer a processor integrated with the FPGA AI engine, and it is also an example of a new category of chips enabled by FPGA.

In summary, with the increased popularization of tasks such as data centers and artificial intelligence, giants like Intel and AMD will examine how to take full advantage of the flexibility of the FPGA to deal with these markets. In the current situation, it is not the best solution to launch FPGA products, but to launch new categories of chips by integrating FPGAs and other chips, which will be an important market direction for FPGA in the future. ‘coming. Next, we will also predict the most critical breakthrough point of FPGA in the future of technical direction.

Enhanced integration and connectivity

As mentioned above, as the FPGA must play a key role in building new chip systems, we believe that integration and interconnection has become an important technical key point. The integration and interconnection here includes two levels: firstly, at the FPGA level, we believe that the FPGA chip itself will integrate more and more related IPS, so as to make the FPGA chip more functional and efficient; The other level is the integration of FPGAs and other chips into the system. We believe that chips and other advanced packaging technologies and related interconnect technologies will be at the core.

First, at the FPGA chip level, the FPGA provides flexibility, but it is inefficient for general modules (such as processors). Therefore, the integration of hard IPs on an FPGA chip to meet the requirements of efficiency and flexibility will continue to be the mainstream idea, and the number of integrated IPs will be more and more in the future. On the same chip, the FPGA is used as the core module, and other hard IP modules (such as CPU, Ethernet, video codec and memory control) are carried at the same time. The NOC and other on-chip interconnect schemes are used to connect the FPGA and other IPS. AMD/xilinx is a pioneer in this field. It can be seen from the wiring diagram of the versal product that more and more hard IP will be integrated on the chip, and Intel’s FPGA will have a similar design in this regard. By integrating these hard IPS, FPGAs will be able to provide more functions. For Xilinx, the most critical IP is the AI-related DSP, and we have also seen new IPs, such as direct RF, which can directly support RF applications through digital-to-analog conversion at very high throughput, and should be combined with FPGA to meet various wireless communication requirements. In this way, true software defined radio can be realized, thus opening up new application scenarios for FPGAs. Therefore, integrating more and more hard IP on the FPGA chip will become an important technical path to further strengthen the FPGA function and enter new application scenarios.

The second level is the integration and interconnection of FPGAs and other chips at the system level. We believe that such integration will be key for FPGAs to enable new systems and classes of chips. Combined with the harder IP integration on FPGA chips mentioned earlier, we believe that FPGAs with increasingly powerful functions can enable more and more new chip categories and open up the market. At this level, we believe that the most critical technology path is to achieve flexible and customizable heterogeneous integration in the form of advanced packaging, complemented by innovative interconnect technologies. In this regard, Intel has previously released the use of advanced packaging technology (emib) to integrate FPGA, high-speed transceiver (for data center scalability interconnect), and DRAM into a single box. At the hotchips conference later this year, Intel also presented a report on using heterogeneous integration to realize innovative RF applications. The main advantage of heterogeneous integration lies in its flexibility. For example, it can be integrated with different types and specifications of chips according to user needs, to maximize the trade-off between performance, cost and customization.

Similarly, amd plans to integrate Xilinx FGPA and CPU. Although no specific technical parameters have been released at present, we believe that the chip technology can also be used according to AMD previous investment in chipet and AMD previous relevant patents.

As the scale of such integration becomes larger and larger, the demand for interconnection becomes larger and larger. Otherwise, the interconnect can become a bottleneck in multi-chip systems. The interconnect must not only provide high bandwidth, but also support important system-level functions such as cache and memory coherency. Currently, Intel and AMD FPGAs support the corresponding CXL protocol. We believe that with larger-scale integration between FPGAs, processors, and other chips, increasingly complex, high-speed inter-chip interconnect will become a key technology.

Software will be the key

Besides the hardware, the most efficient use of the FPGA in practical tasks is also an extremely critical issue. Since the FPGA and other chips (such as the CPU) are tightly integrated to form a heterogeneous chip system, how to ensure that the software can make full use of the FPGA and avoid scheduling bottlenecks is a very complex but important problem. This is a very difficult problem because the programming model of the FPGA and other parts of the system (like the CPU) can be very different. Therefore, how to ensure that the software can properly distribute tasks (that is, assign FPGA-suitable tasks to the FPGA and other processor-suitable tasks to the corresponding processors), reasonably manage the planning and management memory, and provide a user-friendly form for software engineers, it’s a big project. These tasks are quite different from traditional tasks FPGA software (i.e. mainly for front-end and back-end logic synthesis tasks).

In this area, Intel and AMD actively invest. For example, on the UIP roadmap published by Intel, open and flexible software ecology is an important area of ​​investment for Intel. As a result, Intel has just announced that it will acquire Codeplay, a cross-platform heterogeneous chip software compiler. This decision is also seen by the industry as an investment in the next generation FPGA software. At the same time, amd also said at the financial reporting conference in May that it will invest vigorously in the software area, which obviously also includes research and development of FPGA-related software. We believe that as the FPGA becomes an important part of the new chip system, the corresponding software ecology must also keep pace, in order to ensure that such a new FPGA system paradigm truly enters the mainstream. .

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